In the environment of a data processing system with hierarchical memory, the present invention relates to an error control system for named data.
In the prior art many error detecting and error correcting codes have been evolved to insure the integrity of the data to be processed. Generic to all of these codes is redundancy, wherein additional bits are added to the data bits as a function thereof to permit an algorithm controlling the check bits to be recomputed as desired for error detection and possible correction.
One class of codes, known as single error correction, double error detection (SEC/DED) is described by R. W. Hamming in "Error Detecting and Error Correcting Codes," Bell Systems Technical Journal, 29, 1950, pages 147-160.
In the preferred embodiment thereof, the present invention utilizes an error control code of that class although more or less sophisticated codes could likewise be used.
It is also well known in stored program systems to encode not only the information content of a data word stored therein, but also to encode the physical address of the data word along with the data word. While the encoded word consists of data, physical address, and check bits, only the data and check bits are stored. Thus, data stored at incorrect addresses as well as incorrect data bits are readily detectable. See for example, L. S. Tuomenoksa, U.S. Pat. No. 3,231,858 issued Jan. 25, 1966.
However, the prior art systems such as that typified by Tuomenoksa do not function well in a hierarchical memory system since a different encoding would be required for each level of memory due to addressing changes at each level. Furthermore, the error control mechanisms therein described would not provide a continuity check on both the data word and its associated address as the data word is transferred from one level of memory to another and back again to the data source or other elements external to the memory system. The continuity check would not exist because code conversion would be required as data passed from one memory level to another.
Therefore, it is an object of the present invention to provide an improved error control system for hierarchical memory environments.
It is a further object of the invention to provide in a hierarchical memory environment an improved error control system for encoding information relating both to the information of data words and to the address associated therewith.
It is yet another object of the invention to provide an error control system covering both data and associated addressing information in a hierarchical memory environment requiring solely a single encoding for each data word and assuring continuity checking on information transferring between memory levels.
It is still yet another object of the invention to provide an error control system for a hierarchical memory environment having capability for inherent detection of errors incurred in address translation, in transfer of data between memory levels and in fetching of wrong data.